Force-directed scheduling for the behavioral synthesis of ASICs

The HAL system described performs behavior synthesis using a global scheduling and allocation scheme that proceeds by step-wise refinement. The force-directed scheduling algorithm at the heart of this scheme reduces the number of functional units, storage units, and buses required by balancing the concurrency of operations assigned to them. The algorithm supports a comprehensive set of constraint types and scheduling modes. These include: multicycle and chained operations; mutually exclusive operations; scheduling under j x e d global timing constraints with: minimization of functional unit costs, minimization of register costs, minimization of global interconnect requirements: scheduling with local time constraints (on operation pairs): scheduling under fixed hardware resource constraints; functional pipelining; structural pipelining (use of pipelined functional units). Examples from current literature, one of which was chosen as a benchmark for the 1988 High-Level Synthesis Workshop, are used to illustrate the effectiveness of the approach.